In general, the present invention relates to a solid-state image sensing device which employs solid-state image sensing elements which serve as area or linear sensors. In particular, the present invention relates to a solid-state image sensing device which clamps a signal output by a solid-state image sensing element thereof to a predetermined reference potential.
In a solid-state image sensing device employing CCD solid-state image sensing elements such as CCD linear sensors as shown in FIG. 1, differential operations are carried out at a signal processing unit 15 at a later stage by clamping a black level or holding samples in order to compensate for an offset due to the optical transmission through a CCD shift register (serving as an electric-charge transferring unit) 13 for transferring signal electric charge read out from a sensor array 11 and to cancel dark-current components.
An actual circuit configuration of the signal processing unit 15 is shown in FIG. 2. Here, by the black level, the level of picture element signals at shading units 11a and 11b which are also referred to as optical black (OPB) units at the sensor array 11 is meant. The shading units 11a and 11b are also referred to hereafter as a second OPB unit and a first OPB unit respectively.
In order to process digitally a signal output Vout, an A/D converter 16 is provided at a later stage of the signal processing unit 15. The signal output Vout, a clamped output of a clamp circuit 22, is converted into a digital signal by the A/D converter 16. In this case, by setting the clamp level of the clamp circuit 22 at a reference potential Vref of the A/D converter 16, a wide input D (dynamic) range of the A/D converter 16 can be utilized. In general, the reference potential Vref of the A/D converter 16 is set at the maximum level of the input D range.
When only the picture element signal output by the first OPB unit 11b is clamped to the reference potential Vref of the A/D converter 16 in the clamp processing of this black level, a dark current and offset due to the optical transmission through the CCD shift register 13 may be raised to a higher level. In this case, the signal level at the empty transmission unit 13a of the CCD shift register 13 becomes higher than the level of the picture element signals of the OPB units 11a and 11b by a difference caused by the dark current and the like. Accordingly, if its clamped output is supplied to the A/D converter 16 as it is, a signal voltage higher than the reference potential Vref, which is set at the maximum level of the D range, will be input to the A/D converter 16. As a result, such a configuration gives rise to problems that the A/D converter 16 does not function correctly and data resulting from the A/D conversion is therefore damaged. On the top of that, if the worst comes to the worst, the A/D converter 16 itself is damaged.
In addition, the signal output by the empty transmission unit 13a of the CCD shift register 13 can also be clamped to the reference potential Vref of the A/D converter 16. In this case, the D range of the A/D converter 16 that can be used for the signal becomes narrower by the dark-current portion. On the top of that, when the dark-current portion changes due to a change in temperature or the like, the level of the image sensing picture element signal is also shifted by a displacement determined by the dark-current portion. As a result, signal processing for subtracting the dark-current portion and the like is required, inevitably making the circuit configuration accordingly complicated.
In order to solve the problems described above, a solid-state image sensing device is disclosed in Japanese Patent Laid-open No. Hei 7-30820 with a configuration wherein a timing generator 17 generates clamp pulses xcfx86CLP1 and xcfx86CLP2 for clamping the signals of the empty transmission unit 13a of the CCD shift register 13 and the OPB unit 11b on the rear side of the sensor array 11 respectively each over a period of time corresponding to one picture element as shown in timing charts of FIG. 22. The clamp pulse xcfx86CLP1 is set with clamp timing for a signal portion of a signal output by the empty transmission unit 13a of the CCD shift register 13 corresponding to the first picture element while the clamp pulse xcfx86CLP2 is set with clamp timing for a portion of a signal output by the OPB unit 11b on the rear side of the sensor array 11 corresponding to the second picture element or a subsequent one. On the other hand, the A/D conversion is carried out by the A/D converter 16 on a later stage with timing not to sample a portion of a signal output by the empty transmission unit 13a of the CCD shift register 13 corresponding to the first picture element.
It should be noted that notation xcfx86ROG shown in timing charts of FIG. 22 denotes a read gate pulse which is applied to a shift gate 12 for reading out signal electric charge from the sensor array 11. Notations xcfx86H1 and xcfx86H2 are transfer clocks of the CCD shift register 13 whereas notation xcfx86RS is a reset pulse for resetting an detecting unit 14. Notation xcfx86SH is a sample/hold pulse for a sample/hold circuit 21 of a signal processing unit 15. Notation Va is a sample/hold signal output by the sample/hold circuit 21 whereas notation xcfx86CLP (strictly speaking, notations xcfx86CLP1 and xcfx86CLP2) are clamp pulses of a clamp circuit 22. Notation Vout denotes a signal output. In the conventional solid-state image sensing device with the configuration described above, a portion of a signal output by the empty transmission unit 13a of the CCD shift register 13 corresponding to the first picture element is clamped by the clamp pulse xcfx86CLP1. However, a technique for preventing a signal voltage higher than the reference potential Vref of the A/D converter 16 from being supplied to the A/D converter 16 over an entire period of the empty transmission is not taken into consideration.
When signal electric charge is read out from the sensor array 11 to the CCD shift register 13 by application of the read gate pulse xcfx86ROG, by halting transfer clock signals xcfx86H1 and xcfx86H2, the transfer operation carried out by the CCD shift register 13 is suspended temporarily. In this transfer suspension period, no signal electric charge is injected into an FD unit of the electric-charge detecting unit 14. On the top of that, by applying a reset pulse xcfx86RS, a reset state is established, putting the detection output of the electric-charge detecting unit 14 at the highest potential. As a result, by merely clamping a portion of a signal output by the empty transmission unit 13a corresponding to the first picture element using the clamp pulse xcfx86CLP1, a high voltage (a) in the transfer suspension period generated thereafter is supplied as it is to the A/D converter 16 as a signal output Vout.
In addition, in the case of the conventional technology described above, the operation to clamp a portion of a signal output by the empty transmission unit 13a corresponding to the first picture element using the clamp pulse xcfx86CLP1 prevents a signal voltage higher than the reference potential Vref of the A/D converter 16 from being supplied to the A/D converter 16 only during a minimum unit time of the empty transmission period. On the other hand, the A/D converter 16 does not sample a portion of a signal output by the empty transmission unit 13a corresponding to the first picture element. As a result, a signal voltage higher than the reference potential Vref of the A/D converter 16 is not supplied to the A/D converter 16. In order to implement this scheme, however, the sampling time of the A/D converter 16 must be set so that a portion of a signal output by the empty transmission unit 13a corresponding to the first picture element is not sampled, giving rise to a difficulty that it is necessary to modify the sampling time of the A/D converter which is implemented by an externally attached circuit.
In addition, if a reset is applied in the course of transferring signal electric charge by setting the reset pulse xcfx86ROG as is the case with a forced reset aiming at, among other things, a change in exposure time, a newly read out signal is added to a residual signal being transferred in the CCD shift register 13. In this case, the picture element signals output by the OPB units 11a and 11b are increased in magnitude by the residual signal portion. As a result, if only a signal output by the OPB unit 11b is clamped, the signal voltages of the image sensing picture element signal portion with no residual signal, the OPB unit 11a and the empty transmission unit 13a become higher than the reference potential Vref as shown in FIG. 23. Thus, much like the case described previously, if the clamped output is supplied to the A/D converter 16 as it is, the A/D converter 16 will not function correctly and data resulting from the A/D conversion is therefore incorrect. In addition, the A/D converter 16 itself could be damaged in an extreme case.
The present invention addresses the problems described above. It is an object of the present invention to provide a solid-state image sensing device wherein a signal output by a solid-state image sensing element employed thereby is clamped to a predetermined reference potential so as to eliminate an adverse effect on an A/D converter at a later stage.
A timing generator employed in a solid-state image sensing device according to one aspect of the invention has a configuration wherein clamp pulses are generated for clamping a signal portion corresponding to at least one picture element of an OPB unit on the rear side in a signal output by a solid-state image sensing element and for clamping a signal output by an empty transmission unit of an electric-charge transferring unit over a period of time covering an inhibit period of transfer clocks.
A timing generator employed in a solid-state image sensing device according to a second feature of the invention has a configuration wherein clamp pulses are generated for clamping a signal portion corresponding to at least one picture element of an OPB unit on the rear side in a signal output by a solid-state image sensing element and for clamping a signal over a period of time between a halfway point of time in a signal output by an OPB unit on the front side and a halfway point of time in a signal output by an empty transmission unit of an electric-charge transferring unit.
A timing generator employed in a solid-state image sensing device according to a third feature of the invention has a configuration wherein clamp pulses are generated for clamping a signal portion corresponding to at least one picture element of an OPB unit on the rear side in a signal output by a solid-state image sensing element and for clamping a signal over a period of time between a halfway point of time in a signal output by an OPB unit on the front side and the end of an inhibit period of transfer clocks for a signal output by an empty transmission unit of an electric-charge transferring unit.
A timing generator employed in a solid-state image sensing device according to still another fourth feature of the invention has a configuration wherein clamp pulses are generated for clamping a signal portion corresponding to at least one picture element of an OPB unit on the rear side in a signal output by a solid-state image sensing element and for clamping a signal over a period of time between a halfway point of time in a signal of the last picture element preceding ahead by one line and the end of an inhibit period of transfer clocks for a signal output by an empty transmission unit of an electric-charge transferring unit.
A timing generator employed in a solid-state image sensing device according to a fifth feature of the invention has a configuration wherein a clamp pulse is generated for clamping at least a picture element signal not superpositioned on a picture element signal obtained from a previous read operation in case an operation to read signal electric charge occurs during a transfer period of signal electric charge.
A timing generator employed in a solid-state image sensing device according to another sixth feature of the invention has a configuration including an inhibit circuit for inhibiting generation of clamp pulses in synchronization with an operation to read out signal electric charge during a transfer period of signal electric charge in case such a read operation occurs.
In the solid-state image sensing device according to the first aspect of the invention, a signal portion output by the OPB unit on the rear side in a signal output by the solid-state image sensing element is clamped so as to detect a signal level of the OPB unit which level serves as a reference of level detection of a dark current and the like. In addition, by clamping the signal output by the empty transmission unit of the electric-charge transferring unit over a period of time including the inhibit period of the transfer clocks of the electric-charge transferring unit, a high signal voltage generated in company with transfer suspension caused by the inhibition of the transfer clocks can be masked out so that the high signal voltage is not supplied to an A/D converter at a later stage.
In the solid-state image sensing device according to a second feature of the invention, a signal portion output by the OPB unit on the rear side in a signal output by the solid-state image sensing element is clamped so as to detect a signal level of the OPB unit which level serves as a reference of level detection of a dark current and the like. In addition, by clamping a signal over a period of time between a halfway point of time in the signal of the OPB unit on the front side and a halfway point of time in the signal output by the empty transmission unit of the electric-charge transferring unit, a signal voltage higher than a reference voltage which signal voltage accompanies a dark current and the like is not generated at all over the entire empty transmission portion.
In particular, in the solid-state image sensing device according to a third feature of the invention, by clamping a signal over a period of time between a halfway point of time in a signal output by an OPB unit on the front side and the end of an inhibit period of transfer clocks for a signal output by an empty transmission unit of an electric-charge transferring unit, in addition to the fact that a signal voltage higher than a reference voltage which signal voltage accompanies a dark current and the like is not generated at all over the entire empty transmission portion, a high signal voltage generated in company with transfer suspension caused by the inhibition of the transfer clocks can also be masked out.
In the solid-state image sensing device according to the fourth feature of the invention, the signal output by an OPB unit on the rear side in a signal output by the solid-state image sensing element is clamped so as to detect a signal level of the OPB unit which level serves as a reference of level detection of a dark current and the like. In addition, by clamping a signal over a period of time between a halfway point of time in a signal of the last picture element preceding ahead by one line and the end of an inhibit period of transfer clocks for a signal output by an empty transmission unit of an electric-charge transferring unit, in addition to the fact that a signal voltage higher than a reference voltage which signal voltage accompanies a dark current and the like is not generated at all over the entire empty transmission portion, a high signal voltage generated in company with transfer suspension caused by the inhibition of the transfer clocks can also be masked out. On the top of that, the signal voltage of the OPB unit on the front side can also be masked out as well.
In the solid-state image sensing device according to a fifth aspect of the invention, when an operation to read out electric charge is carried out in a transfer period of signal electric charge, by clamping at least a picture element signal not superpositioned on a picture element signal output by a previous read operation, the signal voltages of the image sensing picture element signal portion with no residual signal, the OPB unit and the empty transmission unit can be suppressed to a level below the reference voltage. As a result, a reset is applied in the course of transferring signal electric charge so that the signal voltages of the image sensing picture element signal portion with no residual signal, the OPB unit and the empty transmission unit will never exceed the reference voltage even if a newly read out signal is superpositioned on a residual signal being transferred in the electric-charge transferring unit.
In the solid-state image sensing device according to the sixth feature of the invention, when an operation to read out electric charge is carried out in a transfer period of signal electric charge, by inhibiting the generation of clamp pulses in synchronization with the operation to read out electric charge, a reset is applied in the course of transferring signal electric charge so that, even if a newly read out signal is superpositioned on a residual signal being transferred in the electric-charge transferring unit, causing the picture element signals of the OPB units to increase in magnitude by the residual signal portion, the clamping of signals output by the OPB units is not carried out. As a result, the signal voltages of the image sensing picture element signal portion with no residual signal, the OPB unit and the empty transmission unit can be suppressed to a level below the reference voltage.